Integrated Circuits and Embedded Systems

Development and challenges of Chiplet technology

LIU Zhaoyang, REN Bolin, WANG Zedong, LV Fangxu, ZHENG Xuqiang

Integrated Circuits and Embedded Systems, 2024, 24(2): 10-22.

标准名称	发布年份	发起者	数据率 /Gbit·s^-1	延迟 /ns	能效 /pJ·bit^-1	封装类型
NV Link	2016	NVIDIA	25	—	—	桥接
AIB	2018	Intel	2	<5	0.85	桥接
HBM3	2022	JEDEC	6.4	—	0.37	2D/2.5D/3D
Open-HBI	2020	OCP	8	—	<0.4	2D/2.5D
LIPINCON	2020	TSMC, Arm	2.8	<14	.0486	2.5D
BoW	2019	OCP	16	<5	0.7	2D/2.5D
Infinity Fabric	2017	AMD	16	<9	2	2D
CEI5.0	2022	OIF	112	<10	>1	2D
UCIe	2022	Intel	32	<5	<0.5	2D/2.5D/桥接/RDL
小芯片接口总线技术要求	2023	中国电子工业标准化技术协会	32	13	1.5/2.5	2D/2.5D
Chiplet互连接口标准-草案	2022	中国Chiplet产业联盟	128	6	2.5	2D/2.5D

Table 5 Standard of Chiplet interconnect interface

Other figure/table from this article

Table 1 Comparison of Chiplet and SoC technologies
Fig. 1 Chiplet chip under the UCIe1.0 standard
Fig. 2 Typical application scenario of Chiplet
Fig. 3 Intel Xeon Max CPU
Fig. 4 Architecture of AMD Zen2’ CCD^[9]
Fig. 5 Application scenarios of Zen4’ CCD^[10]
Table 2 Characteristics of interconnection technology in three application scenarios
Fig. 6 Single-ended high-speed parallel interface architecture
Fig. 7 Link initialization and training process under UCIe 1.0 standard
Table 3 Summary of advances of high-speed D2D interface in-package
Fig. 8 SerDes under DAC/ADC-based architecture
Fig. 9 SerDes under analog-mixed architecture
Table 4 Summary of advances of high-speed SerDes interface outside-package
Fig. 10 Chip diagram
Fig. 11 EMIB Packaging technology
Fig. 12 Standard D2D packages defined in the UCIe1.0 specification
Figure. 13 Chiplet EDA requirements