Figure/Table detail

Development and challenges of Chiplet technology
LIU Zhaoyang, REN Bolin, WANG Zedong, LV Fangxu, ZHENG Xuqiang
Integrated Circuits and Embedded Systems, 2024, 24(2): 10-22.  

Process
工艺
制程
DR
数据速率
/Gb·s-1
TYPE
类型
TX发射机 RX接收机 POWER
EFFE.
传输能效
/pJ·bit-1
LOSS
损耗
/dB
REFERENCE
参考
EQ
均衡
DRV
驱动器
AEQ
模拟均衡
STRUCTURE
架构
7 nm 112 PAM 4 TRX 6 FIR DAC-SST CTLE/PGA 3 FFE/18 DFE 6.16 43.9 Broadcom, ISSCC 2023[28]
5 nm 112 PAM 4 TRX 6 FIR DAC-SST CTLE/VGA 7BIT ADC+24+
8 FFE/1 DFE
4.63 48 MediaTek, ISSCC 2023[29]
5 nm 224 PAM 4 RX CTLE/VGA ADC+DSP 1.41 31.6 Intel, ISSCC 2022[30]
5 nm 112 PAM 4 TRX 6 FIR DAC-SST CTLE/VGA 7BIT ADC+
30 FFE/1 DFE
4.5 40 Marvell, ISSCC 2022[31]
28 nm 112 PAM 4 TRX 3 FFE CML CTLE/VGA 4 FFE 2.29 20.8 Peking University,
ISSCC 2022[32]
10 nm 224 PAM 4 TX 8 FIR DAC-CML 2.25 Intel, ISSCC 2021[33]
28 nm 200 PAM 4 TX 5 FFE CML 4.63 18 University of California,
ISSCC 2021[34]
7 nm 112 PAM 4 TX 3-7 FIR DAC-
SST/CML
CTLE/VGA 7BIT ADC+
25 FFE/2 DFE
5.9 45-52 Huawei, ESSCIRC
2021[35]
7 nm 112 PAM 4 TRX 4 FIR DAC-CML CTLE/VGA ADC+DSP 6.51 >40 Inphi, ISSCC 2021[36]
7 nm 112 PAM 4 TRX 8 FIR DAC-SST CTLE/PGA 7 BIT ADC+
32 FFE/1 DFE
8.2 26 eTopus Technology,
ISSCC 2021[37]
7 nm 112 PAM 4 TRX 6 FIR DAC-SST CTLE/VGA 7BIT ADC+
8-24 FFE/1 DFE
4.29 38.9 MediaTek, ISSCC 2020[38]
7 nm 112 PAM 4 TRX 4 FFE CML CTLE/PGA 7 BIT ADC+
31 FFE/1 DFE
5.38 37.5 Xilinx, ISSCC 2020[39]
7 nm 10-112 PAM 4 TX 7 FIR DAC-SST 1.56 Rambus, ISSCC 2020[40]
14 nm 100 PAM4 RX CTLE/VGA 8 FFE/1 DFE 1.1 20 IBM, ISSCC 2019[41]
14 nm 128 PAM 4 TX 3 FFE CML 1.3 IBM, ISSCC 2019[42]
10 nm 112 PAM 4 TX 3 FFE CML 2.07 31 Intel, JSSC 2018[43]
14 nm 112 PAM 4 TX 8 FIR DAC-SST 2.6 IBM, ISSCC
2018[44]
16 nm 19-56 PAM 4 TRX 4 FFE SST CTLE/VGA 7 BIT ADC+
14 FFE/1 DFE
9.7 32 Xilinx, ISSCC 2018[45]
16 nm 64 PAM 4 TRX 3 FFE SST CTLE/VGA 1+5BIT ADC+
FFE/ DFE
5.84 29.5 University of Toronto,
ISSCC 2018[46]
Table 4 Summary of advances of high-speed SerDes interface outside-package
Other figure/table from this article