This paper presents a 4~13 GHz programmable divider implemented using a 28 nm CMOS process. The core programmable divider is composed of a 7-stage multi-mode divider （MMD） core （a 2/3 prescaler stage and six cascaded 2/3 units） and an embedded fixed divide-by-two stage. The 7-bit control word is decoded into 2-bit configuration signals （P1， P2） for each unit， which simultaneously determine the chain length and the division operation mode. The 7-stage MMD core achieves continuous integer division ratios from 1 to 255. The fixed divide-by-two stage extends the total division ratio to 2n， ranging from 2 to 510. An orthogonal divide-by-two stage cascaded with the core programmable divider further extends the division ratio to 4n， ranging from 4 to 1020， and generates four-phase I/Q signals. The proposed dual-bit scheme realizes an independent ÷3 mode for the last active unit in the cascaded chain， where the final stage operation state is directly specified by the configuration word. PVT simulations verify the the robustness of the proposed divider. At 13 GHz with a maximum division ratio of 1020， the divider consumes 6.1 mW of power， and the phase noise is -165 dBc/Hz at a 1 kHz offset. The simulation was performed using a 28-nm CMOS process across TT， SS， and FF process corners and temperatures of -55℃， 27℃， and 125℃.