This paper presents the design and extensive wide-temperature characterization of a 10-bit, 1 GSa/s, 8-channel time-interleaved successive approximation register (TI-SAR) ADC fabricated in a 55 nm CMOS process. The converter employs eight asynchronous SAR sub-ADCs and integrates local reference buffering, SRAM and SPI-based data transfer, off-chip mismatch estimation, and on-chip adjustable sampling delay correction. The prototype is evaluated over a wide temperature range using low-frequency and near-Nyquist input tones. The measurement results are analyzed in terms of effective number of bits (ENOB), signal-to-noise ratio (SNR), harmonic distortion, and residual spectral components associated with interleaving. Measurement results show that the ADC achieves an ENOB of 6.37~6.79 bits over the measured temperature range. As the temperature increases from -25 ℃ to 95 ℃, the SNR decreases by 1.35 dB and 1.71 dB for 49.987 8 MHz and 450.012 2 MHz input tones, respectively, with a total power consumption of 22.36 mW. A complete high-temperature calibration record is further used to verify that the timing correction path remains functional under the most severe measured condition. Normalized error-power analysis shows that the high-temperature degradation is mainly associated with increased residual background error rather than deterioration of calibrated interleaving mismatch. These results support wide-temperature robustness evaluation and residual-error diagnosis of TI-ADCs.