As CMOS technology nodes continue to scale down, aging effects such as Negative Bias Temperature Instability (NBTI) have become increasingly significant and have emerged as critical factors affecting circuit reliability. Accurate prediction of the aging-induced performance degradation in integrated circuits can mitigate the risk of in-field failures. A promising prediction paradigm involves the continuous collection of chip operating conditions, including supply voltage, temperature, signal duty cycle, and partial performance-degradation information, and constructing a machine-learning model that uses past degradation observations to forecast future degradation trends. Such a capability aligns closely with the objectives of Silicon Lifecycle Management (SLM), which seeks to monitor, analyze, and optimize chip performance throughout its operational lifetime. In this paper, we propose the Conditional Autoregressive Transformer (CAT), a decoder-only sequential prediction model that, conditioned on chip operating conditions and historical degradation traces, predicts the degradation trajectory over a future time horizon. CAT leverages causal attention mechanisms to capture the temporal dependencies inherent in NBTI aging dynamics, enabling multi-step extrapolation from partial sensor data. Experimental results demonstrate that CAT achieves accurate degradation forecasting, offering a practical solution for SLM-driven reliability management in advanced CMOS technologies.