To address shrinking performance margins in high-speed PCIe interfaces for AI computing chips, this study uses a TPU PCIe Gen5 link as a representative case to establish a four-dimensional stress model encompassing channel loss, jitter, power-supply noise, and transmit equalization. An automated test platform is developed, and Design of Experiments (DoE) together with Analysis of Variance (ANOVA) is applied to enable systematic margin characterization and performance boundary identification. Through measurement and analysis on a TPU PCIe Gen5 link, the results demonstrate that channel loss is the primary bottleneck affecting eye closure, with a contribution of 42%. The loss-jitter interaction contributes 18.7%, revealing the critical vulnerability of significantly amplified jitter sensitivity under high-loss conditions. The BER=1E-12 performance boundary map, derived from the full-factorial experiment, identifies three failure regions that remain undetected by conventional single-variable testing. This methodology achieves a paradigm shift from binary "pass/fail" assessment to quantitative margin analysis, providing a quantitative foundation for the robust design and reliability assessment of high-speed interfaces in AI computing chips.