R2-Layout: known-defect-driven layout retrieval for manufacturing yield analysis

Jiao Tiansheng, Liu Xianshan, Chen Ye, Zheng Feijun

Integrated Circuits and Embedded Systems ›› 2026, Vol. 26 ›› Issue (11) : 62-70.

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Integrated Circuits and Embedded Systems ›› 2026, Vol. 26 ›› Issue (11) : 62-70. DOI: 10.20193/j.ices2097-4191.2026.0089
Special Issue on HIPI ICTS 2026 Integrated Circuits Test Symposium

R2-Layout: known-defect-driven layout retrieval for manufacturing yield analysis

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Abstract

Yield learning and failure analysis often begin with a small set of sites confirmed by scanning electron microscopy (SEM) or electrical analysis. This work presents R2-Layout, a known-defect-driven multi-instance retrieval system that expands physical review from one confirmed site to structurally similar layout regions. R2-Layout combines structure-aware detector descriptor learning, rotation and reflection augmentation, a template-guided candidate heatmap, and local geometric verification. On a controlled benchmark comprising 50 stitched layouts and 400 ground-truth instances, it achieves a center-hit precision of 0.962 6, a center-hit recall of 0.965 0, and an IoU@0.1 recall of 0.970 0. Furthermore, on 300 random queries across six OpenROAD realistic routed-design layouts, center-hit recall and IoU@0.1 recall reach 0.970 0 and 0.973 3 respectively, demonstrating stable query repositioning under complex routed back- grounds. In a real failure analysis case, a layout context around one SEM confirmed bridge defect is used to search 500 μm windows from different dies on the same wafer. Three additional sites are returned for review, and subsequent SEM examination identifies a morphologically similar bridge defect at one site. The case demonstrates an engineering loop from defect localization to similar structure expansion and physical confirmation. Layout similarity is used only for candidate discovery and is not interpreted as a defect label or causal conclusion.

Key words

manufacturing yield analysis / IC layout retrieval / failure analysis / rotation and reflection robustness / candidate heatmap / hotspot-assisted inspection

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Jiao Tiansheng , Liu Xianshan , Chen Ye , et al. R2-Layout: known-defect-driven layout retrieval for manufacturing yield analysis[J]. Integrated Circuits and Embedded Systems. 2026, 26(11): 62-70 https://doi.org/10.20193/j.ices2097-4191.2026.0089

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