Aiming at the problems of large data volume and resource consumption in the hardware implementation of Reed Solomon (RS) decoding,the RS decoder is optimized in FPGA implementation based on the RS(255,223) code in CCSDS standard and Euclid core decoding algorithm.In this design,the multiplier factor matrix method is proposed to convert the multiplication calculation in the finite field to the addition operation,and the exclusive OR operation is implemented in hardware to simplify the amount of hardware operation data. In the implementation of Euclid's core algorithm module,polynomial division circuit and polynomial multiplication circuit are used to design the hardware circuit,which can reduce the computational complexity and effectively save hardware resources.The FPGA test results show that the optimized decoder can effectively decode and has good decoding performance,and can correct up to 16 code data.