Integrated Circuits and Embedded Systems

Development and challenges of Chiplet technology

LIU Zhaoyang, REN Bolin, WANG Zedong, LV Fangxu, ZHENG Xuqiang

Integrated Circuits and Embedded Systems, 2024, 24(2): 10-22. DOI: 10.20193/j.ices2097-4191.2024.02.002

Fig. 9 SerDes under analog-mixed architecture

Other figure/table from this article

Table 1 Comparison of Chiplet and SoC technologies
Fig. 1 Chiplet chip under the UCIe1.0 standard
Fig. 2 Typical application scenario of Chiplet
Fig. 3 Intel Xeon Max CPU
Fig. 4 Architecture of AMD Zen2’ CCD^[9]
Fig. 5 Application scenarios of Zen4’ CCD^[10]
Table 2 Characteristics of interconnection technology in three application scenarios
Fig. 6 Single-ended high-speed parallel interface architecture
Fig. 7 Link initialization and training process under UCIe 1.0 standard
Table 3 Summary of advances of high-speed D2D interface in-package
Fig. 8 SerDes under DAC/ADC-based architecture
Table 4 Summary of advances of high-speed SerDes interface outside-package
Fig. 10 Chip diagram
Fig. 11 EMIB Packaging technology
Table 5 Standard of Chiplet interconnect interface
Fig. 12 Standard D2D packages defined in the UCIe1.0 specification
Figure. 13 Chiplet EDA requirements