Integrated Circuits and Embedded Systems

Real-time efficient dense optical flow accelerator based on FPGA

FENG Yutai, XU Wenyang, CHEN Fan, WANG Jiaxing, TANG Yongming, SUN Hao

Integrated Circuits and Embedded Systems, 2025, 25(6): 78-86. DOI: 10.20193/j.ices2097-4191.2025.0021

架构层数	LUT	FF	DSPs	BRAMs
1层	14 528	11 096	34	34
2层	31 257	22 376	68	137
3层	43 499	33 274	96	187
4层	62 470	47 712	122	219
5层	77 434	57 810	167	252
总资源数	117 120	244 240	1 248	288

Table 3 Comparing hardware resource consumption for different pyramid tiers

Other figure/table from this article

Fig. 1 Multi-scale pyramidal optical flow calculations
Fig. 2 Flow chart of the pyramid LK optical flow algorithm
Fig. 3 Real-time streaming hardware acceleration system with heterogeneous collaborative architecture
Fig. 4 LK pyramid data flow
Fig. 5 Schematic diagram of iterative folding pipeline architecture
Fig. 6 Image temporal gradient convolution kernel hardware
Fig. 7 Pyramid deflation module
Table 1 Error comparison between the proposed hardware architecture and OpenCV-based optical flow algorithm
Fig. 8 Overlay effect of visualization of dense optical flow field for four dataset
Table 2 Hardware resource consumption and performance comparison between the proposed hardware architecture and other advanced FPGA-based implementations of optical flow algorithm
Table 4 Performance of different resolutions under the three pyramids