Figure/Table detail

Development and challenges of Chiplet technology
LIU Zhaoyang, REN Bolin, WANG Zedong, LV Fangxu, ZHENG Xuqiang
Integrated Circuits and Embedded Systems, 2024, 24(2): 10-22.  

Process
制程		 DR
数据速率
/Gb·s-1		 Modulation
信号调制格式		 POWER
EFFE.
传输能效
/pJ·bit-1		 LOSS
信道损耗
/dB		 EQ
均衡策略		 TX Mode
发射机类型		 REFERENCE
参考
Single-Ended Signal D2D Interconnection In-Package封装内单端信号D2D接口
4 nm 32 NRZ 0.44 4 DFE VM Samsung, ISSCC 2023[15]
65 nm 16 NRZ 0.85 12.6 2 DFE — Sejong Uni., JSSC 2023[16]
28 nm 33 PAM3 1.09 3.3 FFE+DFE CML Korea Univ., JSSC 2023[17]
28 nm 10 NRZ 1.29 7.8 FFE+CTLE SST Nanjing Univ., JSSC 2023[18]
28 nm 20 NRZ 1.18 15 4 FFE — Pohang Univ., ISSCC 2022[19]
7 nm 40 NRZ 1.7 8 CTLE — Cadence, ISSCC 2021[20]
65 nm 28 PAM4 0.64 4.3 2 FFE VM Seoul Univ., JSSC 2021[21]
65 nm 32 PAM4 0.97 11.6 2 DFE Time-Based University of Minnesota,
ISSCC 2020[22]
16 nm 25 NRZ 1.17 8.5 Passive EQ CMOS NVIDIA, JSSC 2018[23]
Differential SignalD2D Interconnection In-Package (XSR)封装内差分信号D2D接口
5 nm 113 PAM4 1.55 11.5 FFE+CTLE CML Marvel, ISSCC 2022[24]
7 nm 112 PAM4 1.7 7 5 FIR+CTLE DAC-SST MediaTek, ISSCC 2021[25]
7 nm 106 PAM4 1.55 10 3 FIR+CTLE DAC-SST Rambus, ISSCC 2021[26]
7 nm 112 PAM4 1.24 - 2 FFE+CTLE SST Xilinx, JSSC 2022[27]
Table 3 Summary of advances of high-speed D2D interface in-package
Other figure/table from this article