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中文
Figure/Table detail
SM4 algorithm FPGA implementation and optimization with agile development
NIE Huaihao, HAN Yueping, LI Kexin
Integrated Circuits and Embedded Systems
, 2024, 24(
7
): 80-84.
方案
资源占用
/个
工作频率
/MHz
吞吐量
/(Gb·s
-1
)
代码量
/行
方案1
1831 LUT
353 FF
340
1.20
352
方案2
1796 LUT
301 FF
270
0.76
1 240
HLS
[
9
]
1955 LUT
438 FF
223
0.60
未知
参考文献[10]
7466 LUT
5158 FF
212
0.34
未知
Table 3
Results comparison
Other figure/table from this article
Fig. 1
SM4 algorithm structure diagram
Table 1
Function list
Table 2
Module list
Fig. 2
SM4 architecture
Fig. 3
Terminal calculation results
Fig. 4
General computational model of lock cycles
Fig. 5
32-stage pipeline structure
Fig. 6
Parallel processing architecture
Fig. 7
ROM structure
Fig. 8
Calculation results
Fig. 9
FPGA verification