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Figure/Table detail
SM4 algorithm FPGA implementation and optimization with agile development
NIE Huaihao, HAN Yueping, LI Kexin
Integrated Circuits and Embedded Systems
, 2024, 24(
7
): 80-84.
Fig. 9
FPGA verification
Other figure/table from this article
Fig. 1
SM4 algorithm structure diagram
Table 1
Function list
Table 2
Module list
Fig. 2
SM4 architecture
Fig. 3
Terminal calculation results
Fig. 4
General computational model of lock cycles
Fig. 5
32-stage pipeline structure
Fig. 6
Parallel processing architecture
Fig. 7
ROM structure
Fig. 8
Calculation results
Table 3
Results comparison
