This paper presents a programmable computing-in-memory circuit based on a 4T GC-eDRAM cell, designed for cryogenic applications. First, a dual word-line readout structure is proposed to prevent data corruption in the memory cell. Second, leveraging the characteristic that computational data tends to be zero-biased, a zero-enhanced decoder/encoder circuit is proposed to further reduce read power consumption. Finally, a programmable near-memory computing circuit is implemented, capable of supporting both logic operations and arithmetic operations such as addition, subtraction, multiplication, and division. The design was fabricated and verified using a TSMC 65nm low power process. Experimental results demonstrate that the proposed circuit achieves a maximum speedup of 6× for convolution operations and 12.3× for lightweight data encryption. Within the temperature range of -40 ℃ to 85 ℃, the circuit exhibits superior read, write and computing energy efficiency compared to a 6T SRAM structure. It is worth noting that, as this circuit is based on a GC-eDRAM design, its performance is closely linked to leakage current and refresh frequency. As the temperature is lowered further into the liquid nitrogen range (77 K), the leakage current of MOS transistors is drastically reduced, enabling the refresh cycle to be significantly extended. This maximizes the circuit's energy efficiency ratio, endowing the designed circuit substantial advantages in low-temperature computing applications.

With the rapid development of frontier fields such as aerospace, deep space exploration, and quantum computing, electronic systems are required to operate reliably under extreme temperature conditions, particularly at cryogenic temperatures. Silicon-Germanium Heterojunction Bipolar Transistor (SiGe HBT) have emerged as a promising candidate for wide-temperature-range analog/mixed-signal integrated circuits due to their high performance and compatibility with silicon-based processes. However, existing commercial compact models, such as HICUM and Mextram, exhibit insufficient accuracy at cryogenic temperatures, limiting their applicability. This paper presents an improved Mextram-based compact model for SiGe HBT operating from 80 K to 400 K. Key enhancements include temperature-dependent modeling of ideality factors and saturation currents in both the main current and base current models, as well as the incorporation of a heterojunction barrier effect model. A comprehensive characterization methodology and parameter extraction strategy for DC and RF behaviors across the wide temperature range are also proposed. Experimental validation shows that the proposed model exhibits excellent consistency with measured data, with an average relative error of less than 20% for the DC characteristics, demonstrating its accuracy and practicality for extreme-environment circuit design.

Temperature is a key variable that impacts the performance, reliability, and energy efficiency of modern integrated circuits. Leveraging the low cost and high integration of standard CMOS processes, CMOS temperature sensors have become widely deployed in conventional temperature ranges for consumer, automotive, power/battery-management, and SoC thermal-monitoring applications. Meanwhile, emerging cryogenic electronics,especially quantum computing,drives on-chip thermometry toward 77 K, 4 K, and even sub-kelvin regimes, where continuous sensing across room-to-cryogenic temperatures and calibration portability become major challenges. This paper provides a systematic review of CMOS temperature-sensing technologies spanning room temperature to cryogenic operation. We first summarize mainstream room-temperature implementations, including hybrid BJT/MOS PTAT/CTAT schemes, resistor-based sensors using various TCR elements, and time/frequency-domain readouts (e.g., ring-oscillator approaches), and compare their uncertainty, energy, area, and calibration cost. We then discuss how cryogenic device physics,such as BJT freeze-out, MOS threshold-voltage evolution, and the behavior of SiGe devices,affects transduction gain, linearity, and mismatch/noise. Finally, we survey representative Cryo-CMOS temperature sensors targeting 4 K and beyond, together with their linearization and calibration strategies, and highlight key trade-offs in temperature range, resolution, power, area, and scalability for multi-point thermal monitoring in both conventional SoCs and quantum-control ICs.