The reliability of ULSI/VLSI integrated circuit chips is related to both design and process. In order to make the chip of ULSI/VLSI operate stably during a specific lifetime, it is necessary to evaluate the inherent failure mechanism that affects the reliability of chips. The purpose of the evaluation is to determine the mechanism of technical wear and ensure that the chip has good reliability throughout the product life by improving the design and process processing level. This paper reviews the reliability evaluation standards of inherent failure mechanisms at home and abroad, expounds these inherent mechanisms, summarizes the experiment methods of different inherent failure mechanisms, and puts forward the reliability evaluation requirements of inherent failure mechanisms. The reliability evaluation of failure mechanisms play a role in process development, library construction and engineering services, and will promote the development of domestic qualitied manufacturer certification.

Miniaturization of chip/system dimensions and functional composites have led to an increase in power density, accompanied by the growth in heat generation. Addressing this problem has become a great challenge in thermal design and a current research hotspot. This paper discusses the advantages and disadvantages of traditional heat dissipation techniques, and systematically analyzes the embedded microchannel heat dissipation structures at home and abroad. The article focuses on summarizing the principles, thermal performance and innovative solutions of heat dissipation technology based on embedded microchannel chips. Current domestic and international solutions are analyzed, and we summarize the experiences and conclusions of chip thermal design based on embedded microchannels, along with the challenges faced. Finally, the current status and future directions of chip thermal design research are presented.

As one of the most advanced new high-density packaging processes, TSV has an extremely complex structural process. Currently, there are few quality inspection and reliability evaluation methods for large-scale applications and engineering applications in China, and relevant unified standards have not been fully established. This paper focuses on TSV silicon interposers in 2.5D packaging, which are the relatively mature and reach the industry consensus. Combining its process structure characteristics and front-line data from actual product production testing, the quality inspection method and the reliability evaluation method for TSV silicon interposers based on the forward movement of quality assurance are studied. A mature solution is established for the process quality monitoring, inspection evaluation, reliability assurance, and the establishment of related standards and specifications for TSV process products.

The evolution of electronic products towards miniaturization and intelligence is an inevitable development trend. High-density integrated circuit packaging technology is a key technology to achieve miniaturization of the product. In this paper, the packaging technology of high-density hybrid integrated circuit is studied. The packaging design of high-density hybrid integrated circuit is discussed from the aspects of substrate selection, structure design and heat dissipation design. On this basis, combined with the reliability requirements for non-hermetic hybrid integrated circuits, the article further studies the reliability evaluation method of high-density and non-hermetic hybrid integrated circuits. The effectiveness of the evaluation method is illustrated through practical examples. It can be used as a reference for the quality assurance system construction of domestic non-hermetic integrated circuits.

In order to investigate single-event transient (SET) of 22 nm FDSOI technology, we have built a FDSOI NMOS model based on Sentaurus TCAD and carried out various SET simulations in 22nm FDSOI NMOS. The sensitive region, bias voltage and temperature dependence of SET in 22 nm FDSOI NMOS have been examined. The simulation results show that the sensitive regions in 22 nm FDSOI NMOS are the body region and LDD region near the body region. As the bias voltage increases, the total collected charge is increasing, and the width of drain transient pulse current is declining. Compared to the bias voltage, the effect of operating temperature on SET in 22 nm FDSOI NMOS is not significant.

This paper evaluates the thermal reliability of assembly process of Fan-out Wafer Level Package based on simulation. Firstly, we briefly introduce the critical technologies of Fan-out wafer level package and analyze the possible failure mechanism of these advanced packaging technologies. Then, for a typical package structure based on Fan-out wafer level package technology, the 1/4 structure finite element model is established. The simulation of the critical structure under the typical military thermal cycling condition is conducted. By analyzing the stress and displacement of the key structures of the package, potential reliability vulnerabilities leading to failure of fan-out wafer-level packaging have been identified.

In this study, a series of fan-out wafer-level packaging daisy chain test chips with various dimensions and specifications were fabricated. Temperature cycling tests were conducted on samples under different geometric parameters. Failure analysis of the failed samples was performed using techniques such as metallographic microscopy, scanning electron microscopy (SEM), and energy-dispersive X-ray spectroscopy (EDS). The failure modes of the redistribution layer interconnect structures in fan-out WLP were systematically investigated and summarized. This research provides guidance for reliability evaluation and high-reliability applications of fan-out WLP products.

The use of epoxy adhesive die attach material in integrated circuits is gaining popularity. Die attach epoxy adhesive resin bleed is commonly observed during the curing process. A reliability issue for wirebonding will occur if the material spreads over an area where wirebonding is to be performed. In this paper, an approach involving contact angle measurement is used to determine the mechanism of resin bleed. In addition, the effect of roughness of the substrate on resin bleed is also discussed. Priliminary results suggest that vacuum baking plays a significant role in resin bleed while no correlation was seen with roughness of substrate.