To address the challenges of functional correctness and optimization efficiency in automated hardware design using Large Language Models (LLMs), this paper presents VeriOptima, a two-stage framework that generates efficient gate-level netlists from natural language specifications. The first stage, ReasoningV, is a high-fidelity Verilog generation model that achieves 57.8% pass@1 accuracy on the VerilogEval-Human benchmark, rivaling state-of-the-art industry models. The second stage, CircuitMind, is a multi-agent optimization framework that refines the generated code to human-expert levels of efficiency. Evaluated on TC-Bench, a gate-level benchmark derived from real design competitions, results show that using ReasoningV as a starting point and optimizing with CircuitMind leads to significantly better PPA metrics compared to other LLM-based flows. Ultimately, 55.6% of the optimized implementations match or surpass the efficiency of top human experts. This work provides the first end-to-end solution that systematically overcomes both generation and optimization barriers, paving the way for fully automated, high-quality circuit design.Related code is open-sourced on GitHub.

This paper presents an embedded system based on a domestically produced FPGA and a self-designed ASIC-like architecture for real-time edge deployment. On the software side, a lightweight neural network named NexusEdgeNet is proposed. It achieves 94.22% accuracy on 39 farmland disease categories with only 0.184 MB of parameters. On the hardware side, an ASIC-like accelerator fully described in Verilog is designed. It adopts a distributed on-chip memory structure, eliminating external memory access, and supports arbitrary-shaped convolution, pooling, and fully connected operations. Several optimization techniques are applied, including near-memory parallel computing, pipelining, sliding convolution windows, and double buffering. The accelerator reaches 399 f/s inference speed on the EP6HL130 FPGA, with 85% resource utilization and significantly reduced logic consumption. The system integrates image acquisition, processing, and display, supporting real-time video stream recognition. It maintains high accuracy while achieving excellent real-time performance and resource efficiency. This work provides a practical, low-cost solution for edge computing applications based on domestic FPGAs.

This paper presents an analog front-end circuit for high-speed SerDes receivers, designed to address varying channel losses. Utilizing a transconductance-transimpedance (Gm-TIA) architecture, the circuit implements a continuous-time linear equalizer (CTLE) with a tunable peaking gain of 2.2~12.5 dB at the Nyquist frequency and a variable gain amplifier (VGA) with a gain range of -8~3.5 dB, offering flexibility for different channel characteristics. A complementary transconductance stage is employed to achieve current reuse, enhancing transconductance and power efficiency. A T-coil structure is designed to achieve broadband impedance matching, considering parasitics from ESD, pads, and AC-coupling. Inductive peaking and tunable MOS resistors are adopted to extend bandwidth and enable continuous gain tuning. Fabricated in a 65 nm CMOS process, post-layout simulations show that the front-end achieves a peaking gain of 1.1~11.5 dB at 25 GHz Nyquist frequency, supports 100 Gb/s PAM4 signal transmission, and consumes 12.83 mW under a 1.2 V supply.

In response to the demand for high real-time motion control and multi-axis collaborative precision optimization in the intelligent development of warehouse logistics robots, a logistics sorting robot system based on domestic FPGA acceleration has been designed and implemented. The core of this system lies in hardware-level optimization of key algorithms: utilizing a customized ISP module to process and achieve sorting target recognition, combined with a hardware-accelerated CORDIC algorithm to efficiently complete inverse kinematics solution, ensuring accurate grasping by the robotic arm, employing a cascade PID algorithm integrated with Kalman filtering to generate high-precision multi-channel PWM signals, driving the mobile platform to deliver accurately. Additionally, the system integrates touchscreen human-computer interaction functions and a dual-arm collaborative handling strategy based on LoRa communication and ultrasonic ranging feedback. The experimental results show that the robotic arm's single operation cycle is optimized to 4 seconds, with a grasping accuracy rate of 90%, the mobile platform's positioning accuracy reaches the centimeter level, and the end-effector error of dual-arm collaborative handling is less than 0.5 cm. This design provides a low-cost, high-reliability domestic solution for the logistics sorting field.

To address the high latency of ARM architecture and the limited functionality of FPGA solutions, a collaborative architecture-based image processing system combining FPGA and PC is designed. The system integrates functions such as brightness, contrast, and color temperature adjustment, green screen matting, skin tone ROI, traffic light ROI extraction, and invalid region removal. The host computer builds a web interface using the Python Flask framework to implement parameter configuration and result display, and also extends the gesture recognition functionality. Data interaction is achieved through a USB-UART link, and the core module's processing speed remains stable at 560 Mb/s, significantly improving image processing efficiency and meeting real-time requirements. This system provides high-quality image input for humanoid robot vision front-end, adapting to low-light and occlusion scenarios, with broad application value.

To address the high-precision requirements for resolver excitation current peak control, this paper designs and implements a high-precision excitation current peak control system based on distributed Delay-Locked Loop (DLL) timing control. By integrating a 7-stage low-offset, high-bandwidth Programmable Gain Amplifier (PGA), a 13-bit hybrid-timing-logic-based Successive Approximation Register Analog-to-Digital Converter (SAR ADC), a 12-bit digital Sinusoidal Pulse Width Modulation (SPWM) module employing a bipolar modulation architecture, and three sets of DLL timing control circuits on-chip, a complete closed-loop excitation current control system is constructed. This system achieves precise sampling and dynamic adjustment of the excitation current peak. The experimental results demonstrate that the designed PWM waveform output achieves a resolution of 1.3 ns and an excitation current peak error of less than ±0.934% at a target current of 400 mA, providing an effective solution for resolver excitation current peak control.

In response to the lack of research on a universal architecture for multi robot collaboration systems suitable for FPGA platforms in existing literature, this paper introduces a multi robot collaboration system based on FPGA. The system constructs a communication network between robots based on UART communication protocol, and uses a designed information transmission mechanism to enable FPGA to receive data from all robots and control them. At the same time, to cope with abnormal situations, an alarm mechanism and remote control mode are also designed for the system. After the actual construction of a multi robot collaboration system and the verification of its functions one by one, the feasibility of the design concept of the multi robot collaboration system proposed in this paper has been confirmed.

Wafer manufacturing involves multi-module coordination and strong temporal constraints. Traditional scheduling methods struggle in high-mix production scenarios due to poor adaptability and difficulty in handling complex constraints. To address the dynamic scheduling challenges under strict Just-in-Time (JIT) constraints, this paper proposes an efficient dynamic scheduling scheme named GA-JIT Scheduler, based on a genetic algorithm. The approach models equipment and processes using directed graphs, encoding JIT and other complex constraints into a fitness function. By integrating time-window detection and genetic evolution strategies, a "perception-decision-execution" closed-loop tuning mechanism is constructed to enable rapid responses to dynamic disturbances. This paper verifies the GA-JIT Scheduler using 4 differentiated scheduling tasks from the "9th National Innovation Competition (BeiFang HuaChuang Cup)", with the measured solution times of the four tasks being 93 256.5 s, 15 311.5 s, 13 013.5 s, and 18 470 s respectively. The algorithm satisfies constraints such as equipment exclusivity and JIT (movement≤30 s, residence time ≤15 s), adapts to multiple scenarios, verifies its engineering applicability and scalability in the dynamic scheduling of wafer manufacturing under strict JIT constraints, and provides a feasible solution for wafer manufacturing with high mix and strong temporal constraints.

Aiming at the industry pain points of traditional water quality monitoring equipment, such as high cost, redundant power consumption, weak data collaboration capability and insufficient scalability, this paper designs and implements a low-power water quality monitoring and cloud collaboration system based on Phytium Pi CEK8903. The system uses the fully localized Phytium Pi development board as the core control unit, integrates TS-200 pH sensor, TS-300B turbidity sensor and DS18B20 temperature sensor to build a perception network, and realizes hardware-level low-power optimization through Dynamic Voltage and Frequency Scaling (DVFS) technology. Locally, the software simulates I²C to drive the OLED display module, and realizes cross-device data interaction between Phytium Pi and Arduino through UART protocol, the cloud builds a front-end and back-end separation service based on Flask+Socket.IO architecture, and realizes full-link data synchronization of "edge device-cloud platform-user terminal" with the help of HTTP/Socket.IO dual protocols. The system supports plug-and-play expansion of sensors and hierarchical fault tolerance mechanism. Users can obtain real-time core parameters such as pH value, turbidity and water temperature through Web terminal (PC/mobile terminal) or local OLED screen, and trigger multi-level early warning when parameters are abnormal. Verified by 72-hour laboratory calibration and field simulation tests: standby power consumption is as low as 0.48W (only 1/10 of traditional equipment), the relative error of pH measurement is ≤0.78%, the turbidity detection accuracy is ±30 NTU, the full-link data transmission delay is ≤1 second, and the data packet loss rate is <0.1%. The system breaks through the energy constraints and data island bottlenecks of long-term field monitoring, provides a low-cost and high-reliability nationalized solution for river water quality supervision, refined aquaculture management and industrial wastewater discharge monitoring, and has significant practical value.

Outdoor pond aquaculture feeding yields significantly vary with water quality evaluation, estimation, and control. However, several issues challenge the accuracy of water evaluation, such as inexplicable missing data in acquired parameters and strong coupling and time-lag correlations among multiple parameters. Inaccurate water evaluation results further introduce errors into the estimation and control processes, potentially leading to sudden losses in aquaculture. Therefore, a real-time water parameter monitoring device is firstly designed in this research, featuring an ESP32 microcontroller and an embedded MATLAB application. This device allows real-time data on ammonia nitrogen, dissolved oxygen, pH value, water temperature, and water depth to be transmitted to the cloud platform, specifically the OneNet IoT platform. Based on the device design, an innovative method with VMD-LSTM-XGBoost structure for parameter decomposition and reconstruction to extraction of temporal information among parameters and the supplementation of missing data. Meanwhile, the Sparrow Search Algorithm (SSA) is employed for decomposition numbers optimization. Furthermore, the combination of AHP-CV-normal cloud model is designed to improve the accuracy of water quality evaluation. Finally, an integrated learning model is constructed to improve the accuracy of water quality prediction. This research optimized the decomposition of 4 parameter groups into 34 sets of time-series data based on collected data and completed missing parameter supplementation. The experimental validation shows that the proposed AHP-CV-normal cloud model for water quality assessment achieves a classification accuracy rate of over 98%, demonstrating good feasibility. The designed VMD-LSTM-XGBoost hybrid model achieves a test accuracy of 96.209% on the validation set, demonstrating strong predictive performance. This research provides an effective solution for monitoring water quality parameters, data imputation, water quality assessment, and prediction in the complex environment of outdoor pond aquaculture, offering theoretical support for feeding strategies.

Front-end RTL design is a critical phase determining a chip's performance, power, and area (PPA). Conventional methodologies often prioritize functional implementation, lacking systematic optimization for PPA metrics. To address this, this paper proposes a multi-dimensional RTL optimization approach-the DCAP co-optimization model. This model establishes a framework encompassing four dimensions: Data-path (D), Computation (C), Area-management (A), and Power-management (P). Using the USB 2.0 data link layer as a case study, data throughput is enhanced via a coupled handshake scheme, computational efficiency is optimized using a real-time iterative CRC architecture, area overhead is controlled through resource management, and power consumption is reduced by improving clock gating coverage. Back-end implementation results based on TSMC 65nm technology demonstrate that the design achieves a throughput of 52.3 MB/s (protocol efficiency:87%) in High-Speed mode, with a power consumption of 0.156 mW and an area of 3 333.6 μm². Compared to the pre-optimized design, this represents a 39% reduction in power and a 23% reduction in area. In conclusion, the proposed DCAP model provides a reusable methodological guide for addressing PPA optimization challenges in digital circuit design at the RTL stage.